In a semiconductor module comprising at least two controllable semiconductor switches which are electrically connected in series to form a half-bridge, the series connection between the current paths has a circuit node which is usually at the electrical potential of the output. The power semiconductor chip connected to a positive supply potential of the half-bridge is then often referred to as “high-side chip,” and the power semiconductor chip connected to a negative supply potential of the half-bridge is correspondingly designated as a “low-side chip.” If, in a first switching state, the high-side chip is in the on state and the low-side chip is in the off state, the circuit node is substantially at the positive supply potential. If, conversely, in a second switching state, the high-side chip is in the off state and the low-side chip is in the on state, the circuit node is substantially at the negative supply potential. Consequently, either a positive or a negative supply potential can be fed to the output by means of suitable driving of the power semiconductor chips. When there is a change from the first to the second switching state or from the second to the first switching state, in the system comprising the half-bridge and an intermediate circuit capacitor connected to the half-bridge, including the associated connection lines, depending on the symmetry of the system, unavoidable common- and differential-mode currents occur which can mutually influence one another and as a consequence entail the transmission of interference emissions. As is known from DE 10 2013 210 146 A1, such interference emissions can be reduced by choosing the unavoidable capacitances between the positive supply potential and ground, on the one hand, and the negative supply potential and ground, on the other hand to be as far as possible identical.
If the semiconductor module is intended to be cooled by means of a heat sink, the heat sink is often connected to ground. In this case, it must be ensured that the heat sink is sufficiently insulated from the electrical supply potential. Ceramic substrates metalized on two sides are often used for this purpose, wherein a ceramic layer is arranged between two galvanically isolated metallization layers of the ceramic layer.
In DE 10 2013 210 146 A1, for this purpose, two respectively metallized ceramic layers are arranged between the heat sink and the semiconductor chips from which heat is to be dissipated by the heat sink. In this case, the ceramic layer closest to the heat sink has a lower metallization layer on its side facing the heat sink, said lower metallization layer determining both the capacitance between the positive supply potential and ground and the capacitance between the negative supply potential and ground.
Since two ceramic layers are arranged between each semiconductor chip and the lower metallization layer and on account of the required thicknesses of said ceramic layers, such an arrangement has high heat transfer resistances between the semiconductor chips and a heat sink mounted on the semiconductor module. Moreover, such arrangements are very cost-intensive on account of the respective two ceramic layers on account of the use of material associated therewith and the manufacturing outlay associated therewith.